In designing digital integrated circuits (ICs), it is often necessary to create a high frequency clock from a lower frequency reference clock. Often, data enters an IC at a reference frequency, but the logic in the IC needs to be clocked at a much higher frequency. The higher frequency clock is typically obtained using a phase-locked loop (PLL). For example, in the IC, a clock generator block is employed that references (or locks to) divider states in the PLL to properly phase a clock generator. This means of synchronizing/phasing the clock generator becomes more difficult when the PLL divider states are not observable from outside the PLL. A typical case in which the divider states of a PLL are not observable can occur when one purchases a PLL from a vendor. The vendor provides a pre-laid out section of silicon with all of the PLL components optimized and debugged to be placed in an application specific integrated circuit (ASIC) design. Intuitively, it would seem that it is an easy thing to synchronize the data to one of the phases of the PLL clock, but a problem occurs due to the fact that a PLL has time jitter or wander (hereinafter “jitter”) with respect to the input reference clock. Typically, this time jitter is very small. Nonetheless, the jitter causes the synchronizer to periodically re-phase the clock generator state machine based on the instantaneous phase difference between the reference frequency and the high frequency clock from the PLL.
Accordingly, it would be desirable and highly advantageous to have a method and apparatus for synchronizing a clock generator in the presence of a jittery clock source.